Hi Everyone,
Does anyone have experience driving a 100 kHz PWM with 12-16 bit resolution from a virtex 5? I was planning to use a system clock of 40 MHz which makes this difficult. Any reading material you may be aware of would be very helpful. Thanks in advance.

I'm not an expert in FPGA, but...
As you say, 40MHz is not enough, it only allows 400 counts at 100kHz.
Why are you limiting so much clock frequency? Virtex 5 can do much more, isn't it?